An integrated circuit (IC) system typically has a memory component associated therewith. A memory component may be place on a printed circuit board (PCB) close to the IC, for instance. An IC utilizes a memory component to store temporary state or information to enable the IC to execute other tasks. An IC may be a microprocessor or a logic device. Memory component associated with an IC may communicate via electrical traces of a PCB.
But, one problem arises by way of communicating via PCB traces is negative timing margin. Negative timing margin is caused due to high cross talk and power noise generated by electrical traces on PCB when the IC system is in use. The distance between an IC and the memory component may further exacerbate these problems. Another problem is the limited number of PCB traces that support high performance memory due to area constraint on the PCB. The real estate shortage disallows the system to have enough PCB traces to support the high performance memory.
An inflexibility typically seen associated with the IC system that has a memory therewith is constant data rate speed between the IC and the memory. This eventually limits various applications that may need multiple data transfer capability.
It is within this context that the embodiments described herein arise.